1. Field of the Invention
The present invention relates differential output circuits and particularly to those with reduced differential output variation.
2. Description of the Background Art
Differential transmission circuits of the low voltage differential signaling (LVDS) standard characterized by high speed, low power consumption and low electro magnetic interference (EMI) are used for example for an interface circuit of a digital display that is required to transmit digital data of an image in large amount rapidly.
In a conventional differential output circuit a plurality of output circuits of an LVDS configuration have current adjusting MOSFETs added thereto, respectively, and one of them is used as a dummy output circuit having an output terminal connected to an end resistance to provide high and low levels which are compared with reference output high and low levels, respectively, to provide a desired output level, and to do so, a signal is generated to control the current adjusting MOSFET corresponding to the dummy output circuit and the signal is applied to the other output circuits' current adjusting MOSFETs to automatically adjustment a current (see Japanese Patent Laying-Open No. 2000-134082 for example).
Such configuration allows a differential output circuit having an output circuit capable of steadily producing a low amplitude signal.
As described in the Japanese Patent Laying-Open No. 2000-134082, however, the differential output circuit requires current adjusting MOSFETs and a control signal generation circuit and is also disadvantageous in that one of the plurality of differential output circuits that is used as a dummy output circuit contributes to a complicated circuit configuration.